1. Field of the Invention
Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor (CMOS).
2. Description of the Related Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever-increasing device densities is particularly strong in CMOS technologies, such as in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). Unfortunately, increased device density in CMOS FETs often results in degradation of performance and/or reliability.
One type of FET that has been proposed to facilitate increased device density is a fin-type Field Effect Transistor. More specifically, in FinFETs, the body of the transistor is formed from a vertical structure, generally referred to as a “fin” for its resemblance to the dorsal fin on a fish. The gate of the finFET is then formed on one or more sides of the fin. FinFETs have several advantages, including better current control without requiring increased device size. FinFETs thus facilitate scaling of CMOS dimensions while maintaining an acceptable performance.